Are you an engineer who wants to be a part of Semiconductor Industry, but don't know where to get started? At the RTL Design & Functional Verification Workshop, you will get to know the latest skills i.e. RTL Design, SystemVerilog, UVM in deep detail. How should you get started with your Job search? How should you crack the interviews from core companies? What are the skill expectations of employers? All this will be talked during the FREE session taken by Mr Mr.P R SivaKumar,CEO Maven Silicon.
Who can attend?
Pre-Final/Final Year Students of B.Tech /B.E. from ECE, EEE,TE, Instrumentation
Students of ME/MTech/MS in Electronics/MSc Electronics
Students who have finished engineering from any of the above stream in 2017
Date: 24/06/2018, Sunday
Time: 9 AM to 1 PM
Speaker:Mr.P R SivaKumar,CEO Maven Silicon
Agenda of the workshop
Overview of VLSI Design
IP, Chips and SoCs
Introduction to VLSI Design Flow
Front End Vs Back End
RTL Design using HDL
Verilog Vs VHDL, Overview of Verilog
Functional Verification
System Verilog and UVM based test benches
Code and Functional coverage
Indian Semiconductor Industry
Products and road maps, Job Opportunities, VLSI Finishing school
Q &A Session
Register here: http://www.maven-silicon.com/free-vlsi-workshop-freshers
Please register only at the above link. Once you register, you will receive a confirmation call from us. Post confirmation, the admit card will be generated and sent to your registered email ID. In Case, you don’t receive the confirmation call, please call us on 9108490555/7338454291
Highlights of the Workshop:
1. Knowledge sharing by veteran trainer Mr. Sivakumar (CEO - Maven Silicon) with experience of 20+ years in VLSI industry.
2. Scholarship coupon worth of Rs. 5000/-
3. Participation Certificate
Note:
Entry to the workshop is FREE.
Only candidates with admit card will be allowed.
Limited seats available.
Snacks will be provided.
We look forward to welcoming you!!
